Welcome to DVCon U.S. 2022!

Virtual Conference 
FEBRUARY 28 – MARCH 3, 2022

The safety and well-being of all conference participants is our priority. Please know that our thoughts are with those affected by the COVID-19 outbreak. In response to conditions caused by COVID-19, DVCon U.S. 2022, scheduled to be held in San Jose, CA, USA on February 28-March 3 will now be held virtually.

The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows. 

The 2022 Program Grid is Now Available!

Important Deadlines

December 6, 2021

Author / Speaker Registration Deadline

January 4, 2022

Draft Presentation Slides Due

January 14, 2022

Final Slides/Poster, Copyright Form, and Video Recording Due

Keynote Speaker

Unleashing AI/ML for Faster Verification Closure

Design verification is one of the most expensive and time-consuming activities undertaken in electronic system development. Advances in machine learning (ML) algorithms, software and practices in the last few years have given verification engineers a powerful suite of tools to attack this problem. Verification tool builders have leveraged these ML advances to accelerate coverage closure, generate better simulation distributions, and improve core verification algorithms. We will explore how exploiting supervised, unsupervised and reinforcement learning have enabled order of magnitude gains in closure convergence and verification cycle reduction.

Become a Sponsor or Exhibitor Today!

For vendors of design and verification tools, IP/VIP, and services, the choice to become a sponsor or participate in the virtual exhibition at DVCon U.S. 2022 is an easy one. DVCon U.S. attendees are among the best and brightest in the design and verification industry. They understand that the products that are highlighted at this conference can potentially help them do their jobs better, so they come prepared to listen and learn. The virtual DVCon U.S. exhibit area will offer opportunities to connect for one-on-one discussions between vendors and the expert users attending the conference, as well as information gathering through the exhibitor’s customized pages. Exhibiting on our virtual platform at DVCon U.S. 2022 is an excellent way to make extended contact with the very engineers and engineering managers that often help direct purchasing decisions in their organizations. 

Example Topics

VERIFICATION
& VALIDATION
  • Advanced methodologies and test-benches
  • Verification processes, regressions and resource management
  • Debug and analysis of complex designs
  • Multi-language design and verification
  • Hardware/Software co-design and co-verification of embedded systems
SAFETY-CRITICAL DESIGN & VERIFICATION
  • Verification and DO-254 compliance
  • Automotive ISO 26262 Design and Verification Challenges
  • Medical or Industrial Verification Challenges
  • Requirements-Driven Verification Methodologies
  • IP protection and security
DESIGN AND VERIFICATION REUSE & AUTOMATION
  • Bridging verification and validation across multiple engines
  • SoC and IP integration methods and tools
  • Applications of the Accellera Portable Stimulus Standard
  • Configuration management of IP and abstraction levels
  • Interoperability of models and/or tools
  • High-level synthesis from ESL languages
  • Bridging virtual prototyping, simulation, emulation and/or FPGA prototyping
MACHINE LEARNING AND BIG DATA
  • Automating the Optimization of Verification Processes
  • Coverage metrics and data analysis
  • Performance modeling and/or analysis
MIXED-SIGNAL DESIGN & VERIFICATION
  • Mixed-signal design & verification techniques
  • Real-value modeling approaches
  • Application of mixed-signal extensions for UVM
LOW-POWER DESIGN & VERIFICATION
  • Low-power design and verification
  • Clock domain crossing verification
  • Power modeling, estimation and management

Gold Sponsors

Best Paper Award Sponsor

Registration Sponsor

Tutorial Sponsors

logo_synopsys
Siemens-logo-website
imperas-web-logo_2

Workshop Sponsors

Siemens-logo-website
breker-logo4
Agnisys-logo-RGB
logo_synopsys
Verliab_Logo_RGB-Color

Exhibitors

Agnisys-logo-RGB
Scientific Analog, Inc.

Conference Sponsors

Global Sponsors

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