Oral/Lecture

Evaluating the feasibility of a RISC-V core for real-time applications using a virtual prototype

The replacement of a key component within industrial embedded systems usually requires huge verification and validation efforts. Especially the replacement of the MCU core architecture normally entails significant changes to the HW/SW co-design and co-verification process, possibly including the purchase of costly design and verification IP. Our intended use-case is a system redesign where an established MCU is replaced by a RISC-V core. Since the complete redesign process requires a significant effort, a feasibility evaluation study helps to elaborate the system requirements and to detect possible issues early in the replacement process. Once feasibility has been demonstrated, hardware (re-)design may start. In this paper we propose a HW/SW co-verification methodology to evaluate the feasibility of an MCU core replacement based on a virtual prototype, thereby saving time and cost for the redesign process. This methodology links the VP development process with the requirements management process to re-use the test cases.

Juan Santana, Fraunhofer IIS/EAS
Gabriel Pachiana, Fraunhofer IIS/EAS
Thomas Markwirth, Fraunhofer IIS/EAS
Christoph Sohrmann, Fraunhofer IIS/EAS
Bernhard Fischer, Siemens AG
Martin Matschnig, Siemens AG

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