Extension of the power-aware IP reuse approach to ESL
Early analysis of the Systems-on-Chip (SoC) energy consumption is an increasingly important topic. In addition to estimating “raw” power consumption, it is important to be able to easily test the impact of power management strategies on power consumption of different use-cases. As for other areas in SoC development, reuse of power-aware models become a key part of quick development of new architectures. In this paper, we present a way to extend IP-reuse capabilities at system level with the reuse of IP power intents. For this purpose, we use SystemC / TLM2.0 performance models and a library called PwClkARCH for power modeling and estimation. This methodology allowed us to easily reuse an interconnect IP as a power and clock aware macro across multiple platforms in NXP’s i.MX8 SoC family. In addition, we were able to correlate the simulation results with actual silicon measurements with about 95\% accuracy. We also applied this approach to our next-generation SoC platform and derived initial power estimates.