Sponsored Workshop

IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 90 minutes!

Agnisys
System-on-chip (SoC) projects are naturally complex, and difficult to complete successfully in a short span of time and with limited resources. From the specification, architecture, RTL design, and software design to verification and validation, all aspects are challenging. This workshop will focus on the challenges faced by designers, driven by the convergence of applications onto a single SoC device, and will suggest methodology improvements using a revolutionary multi-platform solution, such as IDesignSpec NextGen™ (IDS-NG), for creating IPs, stitching them together into an SoC, building software and test sequences for the entire design, and documenting it. Following are the must-have features in any SoC project, which will be discussed in this workshop:
  • End-to-end automation
    • Easy mechanism for generating IP blocks with minimal time and effort
    • Generated code not encrypted and indistinguishable from hand-crafted code
    • Ability to target multiple aspects (firmware, verification, validation, and documentation)
  • Ability to reuse the IPs
    • Customizing the designs
      • Example: adding functionality such as additional fields and registers to the IP’s reg-map
    • Configuring the designs
      • Example: setting values for the parameters
  • Ability to handle different bus protocols for high performance data transfers
  • Horizontal and vertical reuse
    • Verification is not the end: firmware, prototype, and validation are also required
    • Test sequences and register specifications created at block or IP level can be run at subsystem or system level
      • Changes in bus protocol
      • Differences in configuration
      • Differences in the way transaction are carried out
  • Multiple people should be able to collaborate on a project
    • Teams must be able to keep track of changes
IDS-NG is one such cross-platform Integrated Development Environment (IDE) that helps users to create SoC specifications at an enterprise level. It handles individual IP to sub-system to SoC level and is compatible with Word, Excel, IP-XACT, RALF, CSV, and SystemRDL. This workshop will deep dive into an SoC design and complete it from start to finish, considering safety-critical design, verification, firmware, and documentation aspects. It will show how automated SoC assembly techniques are emerging as the preferred approach for reducing manual assembly and integration of IPs, and boosting productivity of SoC design teams significantly further, leading to faster time-to-market for competitive advantage. Since creating a fully validated design requires a strenuous effort from several teams working together, this workshop will help attendees learn how to automate their development process such that there is zero redundancy and zero debug time. It will take a sample SoC design and create it in RTL, stitch it together with a CPU core and other IPs, verify it with UVM, and validate it in a bare-metal C-UVM environment. All in the span of 90 minutes!

Amanjyot Kaur
Agnisys

amanjyot

Neena Chandawale
Agnisys

BCCFC8C1B3A0428191A821B17DAFF762

Anupam Bakshi
Agnisys

5E46561E3D314D70AAE58E5A6560B076

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