IP packaging and qualification are an integral part of IP integration into SoC. Higher turn-around times (TAT) to integrate Graphics IPs into SoC has been a constant challenge in the past. Inefficiencies in package generation, undocumented hacks/workarounds and lack of automation are few of the causes resulting in low quality IP drops. In addition, there weren’t any efficient methodologies to check IP design quality against Industry and SoC standards. This required substantial manual effort to generate IP package and thorough testing at IPs before making an SoC delivery. In this paper, we introduce a novel Tools, Flows and Methodology (TFM) agnostic approach to automated IP packaging along with a sophisticated Quality Assurance (QA) as well as a Quality Checker (QC) infrastructure aiming to shift-left identification of integration bugs using a Continuous Integration (CI) system. The methodology is based on robust and improved methods which can generate fully qualified drops to help reduce SoC Integration TAT from 2-3 weeks to less than 3 days per milestone drop. Within a Product Life Cycle (PLC), there has been around one quarter savings and 50% reduction in resourcing through these efforts.