Oral/Lecture

Maximizing Formal ROI through Accelerated IP Verification Sign-off

Over the past few years, formal verification (FV) has become an essential piece of our verification sign-off methodology. We have successfully used FV to sign off several critical design blocks with zero escape and have also set up a mature FV sign-off flow which is well integrated into our mainstream verification process. However, despite all the great Return on Investment (ROI) generated on each individual block signed off using FV, the overall impact to previous projects was somehow limited due to the scope of FV adoption. To unleash the full power of FV, we believe that 1) FV should be considered as primary method to achieve block-level verification sign-off and 2) FV should also be leveraged at higher-level to uncover “superbugs” which are beyond the reach of traditional simulation approach. This idea is supported by our management team. As a result, we started to deploy FV on a much larger scale to accelerate verification sign-off of a brand-new IP. This paper shares our recent experience on how we upscale FV usage to maximize formal ROI.

Hao Chen, Intel Corporation
Kamakshi Sarat Vallabhapurapu, Intel Corporation
Scott Peverelle, Intel Corporation
Rosanna Yee, Intel Corporation
Hee Chul Kim, Intel Corporation
Johann Te, Intel Corporation
Jacob Hotz, Intel Corporation

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