MatchLib is a SystemC based throughput accurate communication package developed by Nvidia and available as open-source. It can be used to model common buses like AXI. It enables much faster simulation of a design while retaining throughput accuracy. At some point in the design cycle one or more processors will be included in the design, along with software. This workshop will describe how to bring a processor into a MatchLib design in 3 forms: host code execution, fast processor model, and RTL. We will walk though examples using the RISC-V Rocket core, a MatchLib modeled interconnect, and a simple inferencing application. The inferencing application will be run in simulations both as an abstract model in SystemC and as RTL. We will use High-Level Synthesis to create the RTL from the SystemC implementation. This workshop will show the example design running at different levels of abstraction, exploring the different verification objectives that can be achieve at each stage of the design process.