Program Grid

All times are listed in PST. Please note that the program is tentative and subject to change. 

  • Monday, February 28
  • Tuesday, March 1
  • Wednesday, March 2
  • Thursday, March 3
9:00 - 11:00 PSS In The Real World
11:00 - 11:30 Break
11:30 - 12:30 UVM-AMS: An Update on the Accellera UVM IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 90 Minutes! In-Emulator Randomized Testbenches to Revolutionize Functional Verification Performance
12:30 - 13:00 Break
13:00 - 14:00 An Overview of Security Annotation for Electronic Design Integration (SA-EDI) Standard Estimating Power Dissipation of End-User Application on RTL
14:00 - 14:30 Break
14:30 - 15:30 FuSa: An Update on the Accellera Functional Safety Standard Introduction to the 5 levels of RISC-V Processor Verification
15:30 - 17:00 Networking
8:30 - 8:45Opening Session
8:45 - 9:00Break
9:00 - 10:30Portable Stimulus Standard (PSS)Mixed Signal VerificationMemory and Cache Verification
10:30 - 12:00Posters
12:00 - 12:30Break
12:30 - 13:30Sponsor Sessions (Cadence, Imperas & Synopsys) / Networking
13:30 - 14:00Break
14:00 - 15:00KEYNOTE: Manish Pandey
15:00 - 17:00Automating Stimulus GenerationFormal Verification 1Potpourri
8:30 - 9:30Panel: The Meeting of the SoC Verification Hidden Dragons
9:30 - 10:00Break
10:00 - 12:00Regression Runtime and Debug OptimizationFormal Verification 2Automation and Other Languages
12:00 - 13:00Panel: Going Faster - How to Cope with Shrinking Schedules and Increasing Complexity
13:00 - 14:00Birds of a Feather
14:00 - 15:00Sponsor Sessions (AMIQ & Siemens) / Networking
15:00 - 16:30UVM: Knobs & SequencesLow Power and UPFPrototyping
16:30 - 17:00Break
17:00 - 17:30Best Paper Presentation

Conference Sponsors

Global Sponsors

Contact Us